1. Technical Field
The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with an input/output pad (externally connecting electrode) directly above an element formation region.
2. Background Art
Recently, in tandem with the spread of information techniques, an electronic device such as a computer or a mobile phone is required to increase speed as its ability. Accordingly, performance of a semiconductor element represented by a system LSI (Large Scale Integration) having a great effect on performance of the electronic device is inevitably required to further increase speed. However, the increase in speed of the semiconductor element is greatly hampered by a delay of a MOS transistor itself, and a wiring delay of a wiring itself provided as an upper layer thereof and due to parasitic capacity between the wirings.
Conventionally, the delay of the MOS transistor itself is reduced by a miniaturization technique to reduce a gate length. However, as the delay of the MOS transistor itself is reduced due to development of the miniaturization technique, the problem of the wiring delay is brought to the fore. Thus, to reduce the wiring delay, an insulation film having low permittivity (low permittivity film) is used for an insulation film buried between the wirings to reduce the wiring delay.
However, the low permittivity film is considerably reduced in mechanical strength compared to a silicon oxide film conventionally employed. This becomes problematic at the time of assembling process for packaging the semiconductor element, especially at the time of wire bonding process after a diffusion process for forming a circuit with a semiconductor. More specifically, when wire bonding is performed on a pad formed in the semiconductor element, an impact load at the time of wire bonding is transmitted via the pad to an interlayer insulation film provided just under the pad and considerably deforms the interlayer insulation film because the mechanical strength of the interlayer insulation film is not enough. This deformation causes a crack in the interlayer insulation film, which greatly affects reliability of quality of the semiconductor element itself.
Thus, in a conventional example, a metal layer is formed just under the pad with the interlayer insulation film interposed between them, and the formed metal layer and the pad are connected by a connection plug, so that the metal layer receives an impact applied to the interlayer insulation film at the time of bonding. Furthermore, a via prevents the metal layer from being deformed due to the applied impact, in the direction of the impact, in order to improve the mechanical strength of the interlayer insulation film formed just under the pad (refer to Unexamined Japanese Patent Publication No. 2000-114309, for example). As a result, the impact transmitted to the interlayer insulation film at the time of bonding can be reduced, and the interlayer insulation film is prevented from being damaged such as peeled and cracked.
However, according to the above configuration, a stress between the pad provided on a bonding surface of the interlayer insulation film, and the interlayer insulation film is great, and when a film having low permittivity, that is, a low-k film is used for the interlayer insulation film, a crack is generated in the interlayer insulation film at the time of probing, wire bonding, or dicing.
In order to solve this problem, a structure is conventionally proposed as will be described below (refer to Unexamined Japanese Patent Publication No. 2005-116788, for example). FIG. 6 shows a cross-sectional configuration of a semiconductor device according to a conventional example. As shown in FIG. 6, the semiconductor device according to the conventional example has interlayer insulation film 102, interlayer insulation film 103, interlayer insulation film 104, interlayer insulation film 105, and interlayer insulation film 106 sequentially formed on silicon semiconductor substrate 101, and bonding pad 107 formed on interlayer insulation film 106. Here, a plurality of lattice-shaped vias 132, 142, 152, and 162 are provided so as to penetrate the interlayer insulation films 102 to 106 under bonding pad 107, so that they separate the bonding surfaces of interlayer insulation films 102 to 106 between a region under bonding pad 7 and a region outside it, and divide the bonding surfaces of interlayer insulation films 102 to 106 in the region under bonding pad 107. Thus, the structure to support bonding pad 107 is proposed by providing vias 132 to 162. Here, the low permittivity film is used for at least one of interlayer insulation films 102 to 106.
It is described that since vias 132 to 162 divide the bonding surfaces of interlayer insulation films 102 to 106 into several parts, the stress to interlayer insulation films 102 to 106 are reduced, so that interlayer insulation films 102 to 106 can be prevented from being peeled, according to this structure.